Tom J. Kazmierski

Tom J. Kazmierski (M’95-SM’10) received the M.S. degree in Electronic Engineering from the Warsaw University of Technology in 1973 and the Ph.D. degree in 1976 from the Military University of Technology in Warsaw. In 1984 he joined the Department of Electronics and Computer Science at the University of Southampton in the U.K., where he pursues research into numerical modelling, simulation and synthesis techniques for computer-aided design of VLSI circuits. In 1990-91 he worked as a Visiting Research Scientist at IBM VLSI Technology Division in San Jose, CA where he developed and patented synchronization techniques for multi-solver simulation backplanes. He has published over 170 papers in journals and international conferences. Tom served as Chair of the IEEE DASC WG 1076.1 (VHLD-AMS), General Chair of Forum for Design Languages (FDL) 2010 and General Chair of Virtual Worldwide Forum for Electronic Design Automation (VW-FEDA) 2011 and Program Chair of FDL 2018.

Associated articles

JTEHM, Articles, Published Articles
Low-Power and Low-Cost Dedicated Bit-Serial Hardware Neural Network for Epileptic Seizure Prediction System
  This paper presents results of using a simple bit-serial architecture as a method of designing an extremely low-power and low-cost neural network processor for epilepsy seizure prediction. The proposed concept is based on a novel bit-serial data processing unit (DPU)... Read more
JTEHM, Articles, Published Articles
Design and Study of a Smart Cup for Monitoring the Arm and Hand Activity of Stroke Patients
  This paper presents a new platform to monitor the arm and hand activity of stroke patients during rehabilitation exercises in the hospital and at home during their daily living activities. The platform provides relevant data to the therapist in order... Read more